1. Technical Field
The embodiments described herein relate to a delay locked loop (DLL) circuit, and more particularly, to a DLL circuit to produce a multiphase clock signal and a memory device having the same.
2. Related Art
In general, in a synchronous dynamic random access memory (DRAM) device, a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit are employed to produce a clock signal having multiphases. The PLL and DLL circuits produce an internal clock signal that is converted into a reference clock signal in phase with the internal clock signal by a predetermine time. Accordingly, the PLL and DLL circuits output data in synchronization with an external clock signal, wherein the reference clock signal is obtained by converting the external clock signal.
Since the PLL circuit requires significant amounts of time to lock onto a specific frequency of an incoming signal, i.e., a phase locking operation, large amounts of current are consumed. Furthermore, since the phase locking operation includes a filter that requires a high capacitance to obtain a stable operation in the PLL circuit, a relatively large circuit area is needed.
The DLL circuit is commonly used much more than the PLL circuit because of jitter characteristics. Particularly, in a high-speed semiconductor memory apparatus, the DLL circuit that produces a multiphase clock signal is essentially required. In order to produce the multiphase clock signal, two loop circuits are required. A first loop circuit is referred to as a reference loop, wherein the multiphase clock signal is produced through the reference loop. A second loop circuit produces a delayed clock signal, which is synchronization with an external clock signal, by combining phases of the multiphase clock signals from the reference loop. Since the reference loop is also made up of another DLL circuit, locking time is relatively long and current consumption increases. Furthermore, since the DLL circuit locks onto a signal having a clock period as much as N times larger than an incoming signal by using a voltage controlled delay line, a harmonic locking problem can be issued due to the restriction of the locking range.